HyperThought™
The Decode-First Architecture for Scalable AI Inference.
HyperThought is Skymizer’s inference-native LPU architecture and licensable IP platform.
Designed around the economics of serving large language models, HyperThought combines purpose-built hardware, the LISA™ instruction set architecture, compiler and runtime technologies, memory optimization, and scalable workload orchestration. From a single Edge AI node to enterprise on-premise systems and Mini Data Centers, it provides one architectural foundation for building differentiated AI inference products.
- Decode-First LPU
- LISA™ ISA
- Compiler + Runtime
- Edge → Mini Data Center
Why HyperThought
Training Silicon Was Not Designed Around the Economics of Serving AI
The infrastructure requirements of continuous inference are different from training. Large-model serving must manage:
- Persistent model-weight access
- KV-cache growth
- Memory bandwidth
- Model capacity
- Token-generation latency
- Variable sequence lengths
- Concurrency
- Power
- Cost per useful inference
HyperThought is built around these conditions from the architecture level upward.
Platform
More Than an Accelerator Core
LPU Architecture
Purpose-built processing architecture optimized for language-model and transformer inference.
LISA™ Instruction Set Architecture
A language-oriented ISA providing a common execution model across silicon, compiler, runtime, communication, and model workloads.
Compiler Technology
Model graph transformation, scheduling, memory planning, operator optimization, quantization / compression support, and hardware mapping.
Runtime & SDK
Software interfaces for loading, executing, integrating, profiling, and managing model workloads.
Memory & Data Movement
Architecture-level optimization for model weights, KV cache, bandwidth, and inter-device communication.
Workload Orchestration
Software and system mechanisms to coordinate inference phases and heterogeneous compute resources.
Decode-first
Purpose-Built for the Phase That Serves Every Token
During decode, the system repeatedly accesses model weights and state while producing tokens sequentially. That changes the optimization target. Instead of designing primarily for maximum training throughput, HyperThought prioritizes:
- Sustained decode efficiency
- Model-memory capacity
- Memory bandwidth utilization
- Data movement
- KV-cache efficiency
- Predictable serving behavior
HTX301 is the first silicon implementation of this decode-first philosophy.
Orchestration
Treat Prefill and Decode as Different Workloads
HyperThought supports phase-aware inference deployment, including heterogeneous architectures in which compute-oriented resources handle prefill and HyperThought-based accelerators handle decode — so system architects can optimize each phase around the resource that fits it best.
- Application / Agent
- Prefill
- KV / State Handoff
- HyperThought Decode
- Tokens
Scale
One Architecture Across Deployment Scales
Edge AI / AI Box
Inference close to the application, device, or data source.
Enterprise On-Premise
Private AI infrastructure inside the enterprise security and data boundary.
On-Premise Rack
Higher-capacity deployments serving larger models and more concurrent workloads.
Mini Data Center
Multiple inference and heterogeneous compute nodes managed as scalable private AI infrastructure.
Start with one node. Grow without rebuilding the architecture.
Licensing
Build Your Own AI Inference Silicon
HyperThought allows semiconductor and system companies to combine Skymizer’s inference architecture with their own product differentiation.
Engagement can include
- LPU architecture
- LISA™ ISA technologies
- Compiler
- Runtime / SDK
- Model enablement
- Software integration
- Architecture customization
- Engineering support
Target partners
- Fabless semiconductor companies
- ASIC / SoC developers
- Automotive silicon vendors
- Edge AI chip companies
- Enterprise accelerator vendors
- Server & appliance manufacturers
- Cloud / NeoCloud infrastructure providers
- Sovereign AI programs
- Domain-specific AI platform companies
Why license HyperThought
Accelerate Your Inference Silicon Roadmap
Shorten Time to Market
Build on an existing LPU architecture, ISA, compiler, runtime, and silicon proof point.
Differentiate Your SoC
Combine HyperThought with your own CPU, I/O, memory, security, connectivity, safety, and domain-specific technologies.
Avoid Software Fragmentation
Use a coordinated architecture across hardware, ISA, compiler, runtime, model integration, and deployment.
Scale Across Products
Use the same architectural foundation from compact implementations to high-capacity systems.
Evaluate with Real Silicon
Use HTX301 as a practical reference platform for software enablement, model testing, system prototyping, and customer validation.
Proof in silicon
HyperThought, Proven in Silicon
HTX301 is the first productized silicon implementation of HyperThought. It demonstrates:
- Decode-first inference architecture
- LISA™ v3
- Compiler-hardware co-design
- Scalable compute-memory design
- PCIe-based accelerator integration
- Enterprise on-premise deployment
- Ultra-large model capacity
- Edge-to-Mini-Data-Center scale
LISA™
The Instruction Architecture for Language Inference
LISA provides the architectural contract between model software and HyperThought hardware. Instead of treating the accelerator as a generic matrix engine, LISA lets compiler, runtime, execution, memory, and communication be designed around language-model inference.
LISA™ v3 — Proven Today
- Current HTX301 ISA
- Decode-first execution foundation
- Current compiler / runtime generation
- Multi-device platform foundation
LISA™ v4 — Building Next
- Mixture-of-Experts
- Multimodal inference
- Agentic inference
- Increased memory bandwidth
- KV-cache efficiency
- 2-bit-class quantization
- Sparsity
- More advanced manufacturing processes
- Larger future implementations
LISA™ v4 is in development. Roadmap technologies and future process implementations are not current shipping specifications.
Strategy
Architecture Before Process Node
HyperThought creates inference efficiency through architecture, memory behavior, compiler optimization, and software-hardware co-design. HTX301 demonstrates the architecture on mature process technology.
Future implementations can use more advanced manufacturing processes to improve density, performance, and energy efficiency while retaining the underlying HyperThought architecture — a stronger long-term story than presenting process node alone as the source of efficiency.
Technical results
Characterization Highlights
Figures are from earlier HyperThought characterization under the stated conditions and are not a specification of any particular product configuration. For current HTX301 platform capability, see the HTX301 page.
Recognition
Industry Recognition
Best IP / Processor of the Year
Most Promising Product
Watch
HyperThought launch
Build Your Own Decode-First AI Platform
Combine HyperThought’s LPU architecture, LISA™ ISA, compiler, runtime, and scalable inference technologies with your own silicon and system differentiation.